This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-096682, filed Mar. 29, 2001; and No. 2002-037327, filed Feb. 14, 2002, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a magnetic random access memory (MRAM) which uses a tunneling magneto resistive (TMR) element as a memory element.
2. Description of the Related Art
In recent years, MRAM (Magnetic Random Access Memory) memory cells, which use a tunneling magneto resistive (hereinafter abbreviated as TMR) effect, have been proposed as information memory elements.
FIG. 33 shows an equivalent circuit diagram of a semiconductor memory device in accordance with the prior art. FIG. 34 shows a schematic cross-sectional view of a TMR element.
As shown in FIG. 33, a bit line 26 and word lines 27 and 28 are disposed so as to be perpendicular to each other, and a TMR element 25 is disposed at the intersection of, among these, the bit line 26 and the write word line 27. One end portion of the TMR element 25 is connected to the bit line 26, and the another end portion is connected to a transistor 14. Further, a gate electrode of the transistor 14 is the read word line 28.
This TMR element 25 is a three-layer structure which is structured from two magnetic layers and a non-magnetic layer which is sandwiched by the magnetic layers. Namely, as shown in FIG. 34, the TMR element 25 is structured by a magnetization fixing layer 41 which is connected to a lower portion electrode 19a, a magnetic recording layer 43 which is connected to the bit line 26 via an upper electrode (not shown), and a thin tunnel junction layer 42 which is sandwiched by the magnetization fixing layer 41 and the magnetic recording layer 43.
Here, the magnetization fixing layer 41 is structured by an anti-ferromagnetic layer and a ferromagnetic layer, and is called a pin layer because the magnetization is fixed in one direction. On the other hand, the magnetic recording layer 43 is structured by a ferromagnetic layer, and is called a memory layer because the direction of magnetization can be freely changed and information is stored. The direction of magnetization of the magnetic recording layer 43 can be changed by a synthetic magnetic field formed by an electric current which flows in the bit line 26 and an electric current which flows in the write word line 27.
FIG. 35 and FIG. 36 show cross-sectional views of a semiconductor memory device in accordance with the prior art. The laminated-structure semiconductor memory device shown in FIG. 35 and FIG. 36 comprises a memory cell section and a peripheral circuit section disposed at the periphery of the memory cell section.
At the memory cell section, an element isolation region 12 having an STI (Shallow Trench Isolation) structure, and, for example, an N-type diffusion layer 13a are selectively formed, for example, in a P-type semiconductor substrate (or well) 11. A MOSFET 14 is selectively formed on the semiconductor substrate 11. First to fifth wirings 16a, 17a, 18a, 19a and 20a are formed in an insulating film 15 on the semiconductor substrate 11. Further, the diffusion layer 13a and the first wiring 16a are connected at a first contact 21a, the first wiring 16a and the second wiring 17a are connected at a second contact 22a, the second wiring 17a and the third wiring 18a are connected at a third contact 23a, and the third wiring 18a and the fourth wiring 19a are connected at a fourth contact 24a. Further, the fourth wiring 19a and the fifth wiring 20a are connected at the TMR element 25. The TMR element 25 is structured by the magnetization fixing layer (magnetic layer) 41, the tunnel junction layer (nonmagnetic layer) 42, and the magnetic recording layer (magnetic layer) 43.
Further, the fifth wiring 20a connected to the TMR element 25 is the bit line 26. The third wiring 18a which is not connected to the fourth wiring 19a is the write word line 27, and the write word line 27 is disposed so as to be orthogonal to the bit line 26. The TMR element 25 disposed at the intersection of the bit line 26 and the write word line 27 is used as a memory element. The MOSFET 14 electrically connected to the TMR element 25 functions as a switching element, and the gate electrode of the MOSFET 14 is the write word line 28. The first wiring 16a which is not connected to the second wiring 17a is a Gnd (ground) line 29.
Operations of writing/reading information in such a memory cell will be simply described.
First, when data xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d are written in the TMR element 25, a pair of the write word line 27 and the bit line 26 are selected, and electric current is made to flow to both of the write word line 27 and the bit line 26 which are selected, and current magnetic fields are respectively generated. In accordance with this, only the magnetic field which is applied to the selected cell positioned at the cross point portion of the write word line 27 and the bit line 26 exceeds an inversion threshold value of magnetization of the TMR element 25, and information is written.
At this time, for example, when the directions of magnetization of the magnetization fixing layer 41 and the magnetic recording layer 43 are parallel, the tunnel resistance detected by making electric current flow to the tunnel junction layer 42 is the lowest, and in this state, for example, xe2x80x9c1xe2x80x9d can be stored. On the other hand, when the directions of magnetization of the magnetization fixing layer 41 and the magnetic recording layer 43 are anti-parallel, the tunnel resistance detected by making electric current flow to the tunnel junction layer 42 is the highest, and in this state, for example, xe2x80x9c0xe2x80x9d can be stored. Namely, in an MRAM, the difference of the tunnel resistances is stored as data xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d.
On the other hand, when the data xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d which are written in the TMR element 25 are read out, when the read word line 28 and the bit line 26 are selected, electric current flows to the Gnd line 19 through the TMR element 25 and the MOSFET 14 from the bit line 26, and a determination of the data xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d is carried out by the peripheral circuit reading out, as information, the difference of the tunnel resistances between the different TMR elements 25.
In the conventional semiconductor memory device having a memory cell section as described above, the peripheral circuit section is provided at the periphery of the memory cell section in order to control the memory cell. The peripheral circuit section will be described hereinafter.
FIG. 35 is an example in which a resistive element is provided at the peripheral circuit section. As shown in FIG. 35, a diffusion layer 32b is connected to wirings 16b via contacts 21b. Here, the diffusion layer 32b in the peripheral circuit section functions as a resistive element 30. The resistance value of the resistive element 30 is improved by enlarging the surface area of the diffusion layer 32b. However, in this case, the chip area becomes large due to the enlargement of the surface area of the diffusion layer 32b. Therefore, it is difficult to aim for miniaturization of the chips.
FIG. 36 is an example in which a fuse element is provided at the peripheral circuit section. As shown in FIG. 36, a diffusion layer 13b is connected to the first wiring 16b via the first contact 21b, and the first wirings 16b are connected to a second wiring 17b via second contacts 22b. The second wiring 17b is connected to a latch circuit (not shown). These wirings and contacts of the peripheral circuit section function as a fuse element 50. In this way, the conventional fuse element 50 is formed in a pattern different from that of the memory cell section. In such a conventional art, accompanying the miniaturization of elements, it has been desired to reduce the area occupied by the fuse element 50 with respect to the chip area.
A semiconductor memory device according to one aspect of the present invention comprises a memory cell section and a peripheral circuit section disposed at a periphery of the memory cell section, the memory cell section comprising a first wiring which is extended in a first direction, a second wiring which is disposed above the first wiring and is extended in a second direction different from the first direction, a third wiring which is disposed between the first and second wirings, and a first magneto resistive effect element which is disposed at an intersection of the first and second wirings between the first and second wirings, and is connected to the second and third wirings, and the peripheral circuit section comprising a fourth wiring, a fifth wiring which is disposed above the fourth wiring, and a second magneto resistive effect element which is disposed between the fourth and fifth wirings and is connected to the fourth and fifth wirings to be used as any of a resistive element, a fuse element, and a contact.